What you will learn
- Introduction to complete VLSI Design flow (FPGA, ASIC and RFIC)
- Linux and advanced Scripting languages: TCL, Perl
- Fundamentals of Circuit theory, Network Analysis and Devices
- Advance Logic Synthesis & Optimization
- Design For Testability and Logic Equivalency Check (Pre & Post Synthesis)
- Static Timing Analysis
- Timing Constraints & Understanding timing Arcs
- Completed Physical Design Flow and DFM
- Advanced Timing and Power Analysis
- DFM, Parasitic Extraction and Post layout simulation
Fee :
- A candidate needs to pay 10,000/- to block the enrollment.
- The remaining fee can be paid in installments within the first month (Before the completion of Module 1 - DVV).
Duration : 5 months :
- 3 months modules & evaluation + 2 months industry oriented project + Soft Skills training
- Mock Interviews to begin from 3rd Month onwards
- Mode: Offline
- Venue: Entuple Technologies
Learning outcomes
At end of the course you will be able to
- Formulate and Apply PVT constraints for logic Synthesis
- Set environment, libraries for the synthesis of the assigned module
- Insert DFT constraints for logic synthesis
- Generate netlist and analyse the synthesis reports to identify trade off
- Perform Logic Equivalence checks and optimise synthesis for PPA * Identify and apply timing arc information from the target library
- Identify cell delays, wire load information to calculate slew degradation and net delaysv
- Apply Setup and hold checks, identifying clock properties and timing paths
- Formulate design level and environmental constraints
- Analyse the reports and resolve timing issues * Enumerate PD flow stages
- Set up and prepare data for the PD flow
- Carryout floor plan and power plan
- Run placement, optimization, clock tree synthesis, and routing on the assigned design
- Carryout signoff checks including post layout STA and write out GDSII
