What you will learn
- Introduction to complete VLSI Design flow (FPGA, ASIC and RFIC)
- Linux and advanced Scripting languages: TCL, Perl
- Fundamentals of Circuit theory, Network Analysis and Devices
- Digital Design using Verilog HDL and Functional Verification
- Formal and Code coverage Analysis
- System Verilog Basics, Data Types & OOP’s concepts
- System Verilog Assertions & Randomization
- UVM Testbench Architecture
- UVM advanced concepts and TLM (Transaction Level Modeling)
- Advance Logic Synthesis & Optimization
- Design For Testability and Logic Equivalency Check
- Capstone project – Layer, Protocols and more
- Mock interviews
Fee :
- A candidate needs to pay 10,000/- to block the enrollment.
- The remaining fee can be paid in installments within the first month (Before the completion of Module 1 - DVV).
Duration : 5 months :
- 3 months modules & evaluation + 2 months industry oriented project + Soft Skills training
- Mock Interviews to begin from 3rd Month onwards
- Mode: Offline
- Venue: Entuple Technologies
Learning outcomes
At end of the course you will be able to
- Enumerate the complete ASIC design flow
- Solve digital subsystem design problems
- Code RTL for the asigned digital blocks using Verilog HDL
- Formulate testbenches and carryout functional verification using simulations
- Carryout the design and verification of the assigned module project and documentation
- Enumerate the need for and the objectives of functional verification
- Formulate test cases for the functional verification of the assigned modules
- Formulate the environment for functional verification of the DUT assigned using OOPs and Classes in System Verilog
- Demonstrate randomization and analyse functional coverage using System Verilog
- Utilize Assertions to correct the behaviour in simulation
- Describe the need for verification methodology
- Enumerate UVM Components, Objects and TLM
- Build test bench components for various modules
- Use DPI with C/C++ in verification environment
- Carryout RAL modelling
